1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Related Art
The ferroelectric capacitor of FeRAM (Ferroelectric Random Access Memory) that is currently mass-produced has the planar structure.
However, the capacitor having the stacked structure that can reduce the cell area smaller is required in future in reply to the request for the higher integration. The stacked structure has the conductive plug, which gives the contact to the semiconductor substrate, directly under the lower electrode of the ferroelectric capacitor. As set forth in Patent Application Publication (KOKAI) 2001-44376, for example, normally the tungsten or the polysilicon is employed as the material of the conductive plug.
Meanwhile, most of FeRAM products are hybridly integrated with the logic product. In the logic semiconductor device, normally the process using the tungsten plug to connect the lower conductive pattern and the upper conductive pattern is employed. The resistance value of the tungsten plug is of course employed as the spice parameter to design the circuit.
Therefore, it is preferable that, with regard to the significances of practical use of accumulated circuit design resources and reduction in development man-hour/cost, the tungsten plug should be employed as the contact plug in the FeRAM, which is hybridly integrated with the logic product, like the prior art.
Next, steps of forming the stacked capacitor that is connected to the top surface of the tungsten plug in the FeRAM memory cell will be explained hereunder.
First, steps required until a structure shown in FIG. 1A is formed will be explained hereunder.
A device isolation insulating film 102 is formed around an element forming region of a silicon substrate 101, and then a well 103 is formed in the element forming region. Then, two MOS transistors 104 are formed in the well 103.
Each of the MOS transistors 104 has a gate electrode 104b, which is formed on the well 103 via a gate insulating film 104a, and impurity diffusion regions 104c, 104d, which are formed in the well 103 on both sides of the gate electrode 104b and act as the source/drain. Also, sidewall spacers 105, which are used to form high-concentration impurity regions 104d in the impurity diffusion regions 104c, are formed on both side surfaces of the gate electrode 104b. 
Then, an interlayer insulating film 107 for covering the MOS transistors 104 is formed on the silicon substrate 101.
Then, contact holes 107a are formed in the interlayer insulating film 107 on one impurity diffusion regions 104c of the MOS transistors 104. Then, a tungsten film 108 is formed in the contact holes 107a and the interlayer insulating film 107.
Then, as shown in FIG. 1B, the tungsten film 108 formed on the interlayer insulating film 107 is removed by the CMP (Chemical Mechanical Polishing) method. Then, the tungsten film 108 left in the contact holes 107a is used as a contact plug 108a respectively.
Then, as shown in FIG. 1C, a first metal film 109, a ferroelectric film 110, and a second metal film 111 are formed on the contact plugs 108a and the interlayer insulating film 107.
Then, ferroelectric capacitors 112 are formed by patterning the first metal film 109, the ferroelectric film 110, and the second metal film 111 by virtue of the photolithography method. In each of the ferroelectric capacitors 112, the first metal film 109 is used as the lower electrode, and the second metal film 111 is used as the upper electrode. The ferroelectric capacitor 112 is the stacked capacitor, and the lower electrode 109a is connected to one impurity diffusion region 104c of the MOS transistor 104 via the underlying contact plug 108a. 
Now, consideration will be given to the contact plugs 108a formed directly under the ferroelectric capacitors 112.
The CMP process is executed at the time of the contact plug formation. At that time, if the tungsten film 108 is still left on the interlayer insulating film 107 after the CMP, short-circuit between the contact plugs 108a may occur. In order to avoid such circumstance, the CMP is executed to attain the slight over-etching. As a result, as shown in FIG. 1B, erosion or recess is generated around the contact plugs 108a to cause level difference, and simultaneously upper surfaces of the contact plugs 108a are polished. This level difference causes a minute concave portion in the lower electrode 109, which exerts a bad influence on the crystallization of the overlying ferroelectric film 110. Thus, in some cases the polarization characteristic of the ferroelectric film 110 is deteriorated.
Also, in the steps of forming the ferroelectric capacitors 112 and subsequent steps, various annealing steps such as the crystallization annealing, the recover annealing, etc. are needed.
Meanwhile, as set forth in Patent Application Publication (KOKAI) Hei 10-303398, when the tungsten is used as the material of the contact plug formed directly under the ferroelectric capacitor, the tungsten plug is oxidized at a very quick speed and at a low temperature to cause the defective contact between the tungsten plug and the lower electrode. Also, when polysilicon is used as the material of the contact plug formed directly under the ferroelectric capacitor, the polysilicon is also oxidized, though not to the degree of the tungsten. The oxidation spreads over the entire contact plug once such oxidation occurs, so that the defective contact is easily caused and thus reduction in yield of the FeRAM device is caused.
In this manner, though various annealing steps are required to improve the performance of the ferroelectric capacitor, nevertheless the temperature must be lowered to some extent so as to cause the contact plug formed directly under the ferroelectric capacitor to operate normally.
As a result, improvement in the performance of the ferroelectric capacitor and improvement in the contact performance of the contact plug are in the trade-off relationship.
In addition, as the technology of maintaining the performance of the ferroelectric capacitor in the prior art, the structure for connecting the contact plug and the lower electrode via the barrier metal and covering the barrier metal under the lower electrode with the oxidation-preventing insulating film is set forth in Patent Application Publication (KOKAI) 2000-138349 and Patent Application Publication (KOKAI) 2000-349252. In order to form such structure, the polishing step of planarizing upper surfaces of both the barrier metal and the surrounding insulating film is added. In this case, like the case shown in FIG. 1B, there is a possibility that, because of difference in the polishing speed between the insulating film and the barrier metal, the erosion and the recess are caused. In addition, the step of forming the barrier metal and the insulating film and the step of polishing the barrier metal are added and also alignment margin of the barrier metal to the contact plug must be considered. Thus, the above structure is unstable for the miniaturization.
Further, to form the oxidation-preventing barrier metal layer in the contact hole and over the conductive plug as the oxidation-preventing structure of the contact plug is set forth in Patent Application Publication (KOKAI) 2000-349255 and Patent Application Publication (KOHYO) 2001-501375. However, according to such structure, it is difficult to assure selectively the space, into which the barrier metal layer is buried, over the contact hole.